This application is based upon and claims the benefit of priority of Japanese Patent Applications No. 2002-000668, filed on Jan. 7, 2002, the contents being incorporated herein by reference.
The present invention relates to a pulse width detection circuit, a DC component cancellation circuit, and a receiving circuit.
Optical communication systems using optical fibers or infrared, which is transmitted through open space, are applied to electronic devices nowadays. In an optical communication system, the receiving circuit receives light, converts the received light to an electric signal, and amplifies the electric signal. The receiving circuit further generates a binary receiving signal from the electric signal. To improve the receiving accuracy, the receiving signal must be generated so that it accurately corresponds to the input signal (received light).
In the prior art, the receiving circuit of an optical communication system includes multiple stages of amplifiers to amplify input signals, which amplitudes are extremely small. The amplitude of an input signal becomes smaller as the distance between a light source and a light receiving device increases. The multiple stages of amplifiers have a total gain that is required to generate a receiving signal from input signals having amplitudes (IPD), for example, between about 100 nA and 10 mA. The receiving circuit generates the binary receiving signal from the amplified signal in accordance with a predetermined threshold voltage.
The receiving circuit includes a filter (differentiation) circuit to extract an edge of the input signal. The filter circuit is arranged between the amplifiers. The receiving circuit generates a pulse signal, which corresponds to the edge position of the input signal, with the filter circuit and amplifies the pulse signal with the amplifiers. The receiving circuit employs the filter circuit to generate the receiving signal with a pulse width that is substantially the same as that of the input signal.
The input signal, which amplitude is large, has a waveform that includes a gradual trailing portion. The amplifiers also amplify the gradual trailing portion. Referring to FIG. 1, in accordance with a threshold value, an input signal having a small amplitude is amplified to generate an amplified signal Sa, and an input signal having a large amplitude is amplified to generate an amplified signal Sb. A binary receiving signal RX is generated from the amplified signal Sa and the amplified signal Sb. The amplified signal has a gradual trailing portion. Accordingly, the receiving signal RX generated from the amplified signal Sb (shown by broken lines) is greater than the pulse signal of the receiving signal RX generated from the amplified signal Sa (shown by solid line).
The filter circuit generates a signal having a first pulse, which corresponds to a rising edge of the input signal, and a second pulse, which corresponds to a trailing edge of the input signal. The waveforms of the rising edge of the first pulse and the trailing edge of the second pulse do not change much even when they are amplified. Accordingly, the receiving circuit uses the rising edge of the first pulse and the trailing edge of the second pulse to generate the receiving signal RX, the pulse signal of which is substantially the same as the input signal.
The filter circuit functions to cancel the offset voltage of the amplifiers. When the multiple stages of amplifiers are connected in series, the output signal of the final stage amplifier includes a DC component that is generated by amplifying the offset voltage of each amplifier. The DC component hinders the generation of an accurate binary receiving signal RX. When the DC component exceeds a threshold value, the receiving circuit generates the receiving signal RX at a constant level (high level). Thus, when amplifying an extremely small input signal (received light), a plurality of filter circuits are employed to eliminate the DC component generated by the amplifiers.
Each filter circuit is a high pass filter (HPF), which eliminates predetermined frequency components of the input signal (e.g., DC component or component from DC to frequency lower than a communication frequency). Accordingly, each of the filter circuits connected between the amplifiers eliminates the effects of the offset voltage of the amplifier in the previous stage.
However, when generating the receiving signal RX using a plurality of filter (differentiation) circuits, the receiving signal RX may be generated erroneously from the input signal Sin, as shown in FIG. 2. A first filter circuit generates a first processed signal S1 in accordance with the input signal Sin. A second filter circuit generates a second processed signal S2 in accordance with the first processed signal S1. The second processed signal S2 includes pulses P1 and P2, which respectively correspond to the rising edge and trailing edge of the first processed signal S1. Accordingly, when the second processed signal S2 is compared with a threshold voltage, the receiving signal RX goes high during the period between the first pulse P1 and the second pulse P2 and after the fourth pulse P4.
In an optical communication system that receives a signal light through open space, a light receiving device receives, for example, solar light together with the signal light. The light receiving device generates a receiving current, which is included in the DC component that results from the solar light. The DC component resulting from the solar light hinders the generation of an accurate receiving signal in the same manner as the offset voltage of the amplifiers.
Thus, the receiving circuit includes a DC cancellation circuit, which is connected between the input and output terminals of the initial stage amplifier (preamplifier). In accordance with the output voltage of the preamplifier, the DC component cancellation circuit generates a cancellation current to cancel the DC component of the current that is input to the preamplifier and feeds back the cancellation current to the input of the preamplifier.
Referring to FIGS. 3A and 3B, the prior art integration type DC component cancellation circuit and the prior art DC component cancellation circuit incorporating a low pass filter (LPF) causes a peak level of an input signal Vin to approach a reference voltage Vref and cancels a DC offset. However, when the input signal Vin continues for a long period of time, the output signal Vout is offset in a direct current manner and increased, as shown in FIG. 3C. This is because the prior art DC component cancellation circuit approximates the average value level of the input signal Vin with the reference voltage Vref. Another reason is in that, as shown in FIG. 4, the average value of the input signal Vin (shown by broken lines) fluctuates (decreases).
It is an object of the present invention to provide a pulse detection circuit that accurately detects the pulse width from the input signal. A further object of the present invention is to provide a current component cancellation circuit that accurately cancels a DC component. A further object of the present invention is to provide a receiving circuit that generates a receiving signal having a pulse width that accurately corresponds with the pulse width of a receiving current.
To achieve the above objects, the present invention provides a pulse width detection circuit for detecting a pulse width of an input signal and generating a binary signal having a pulse width corresponding to the pulse width of the input signal. The detection circuit includes a first filter circuit for receiving the input signal and generating a first processed signal. The first processed signal includes a first component having an AC component of the input signal and a second component having a low frequency component or a DC component of the input signal. A second filter circuit is electrically connected to the first filter circuit. The second filter circuit includes a high pass filter for receiving the first processed signal and generating a second processed signal. A binary conversion circuit is electrically connected to the second filter circuit. The binary conversion circuit receives the second processed signal and generates the binary signal.
A further perspective of the present invention is a method for detecting a pulse width of an input signal. The method includes generating a filtered signal by filtering the input signal with a first high pass filter, generating a first processed signal by adding a low frequency component or a DC component of the input signal to the filtered signal, generating a second processed signal by filtering the first processed signal with a second high pass filter, and generating a binary signal with the second processed signal.
A further perspective of the present invention is a receiving circuit including a first amplifier for converting a receiving current to a voltage signal and a first filter circuit connected to the first amplifier to generate a first processed signal in accordance with the voltage signal. The first processed signal includes a first component having an AC component of the voltage signal and a second component having a low frequency component or a DC component of the voltage signal. A second filter circuit is electrically connected to the first filter circuit. The second filter circuit includes a high pass filter for receiving the first processed signal and generating a second processed signal. A binary conversion circuit is electrically connected to the second filter circuit to receive the second processed signal and generate a binary signal.
A further perspective of the present invention is a DC component cancellation circuit connected to an input terminal and an output terminal of an amplifier that amplifies an input signal and generates an amplified signal. The cancellation circuit eliminates an offset voltage included in the input signal. The cancellation circuit includes a voltage holding circuit for receiving the amplified signal and holding a peak voltage of the amplified signal. A feedback amplifier is connected to the voltage holding circuit. The feedback amplifier compares the held peak voltage with a reference voltage and generates a feedback signal to eliminate the offset voltage. The feedback signal is provided to the input terminal of the first amplifier.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.